At a tech event in China, Intel introduced its biggest Stratix 10 family FPGA chip. It comes with a pretty big milestone with its connectivity technology that can make the silicon very big.

The nature of the repeatable unit design is to understand issues with process technology, and as a result, we often see FPGAs be the largest silicon dies that enter the market for a given manufacturing process. It is notable that until this FPGA design, Intel hadn’t used EMIB to connect together two high powered dies.

Furthermore, the Intel Stratix 10 GX 10M FPGA is approximately 3.7x denser than the Intel Stratix 10 GX 1SG280 FPGA, previously the densest member of the Intel Stratix 10 device family.

Such a chip by Intel is made to use in the professional applications in a test, simulation, and prototyping of the most advanced ASICs, SoC chips, and, measurement, computing, networking, aerospace, defense, etc., with 35 billion transistors.

One of the disparagement as known is that Intel products connect one high-powered and one low-powered die is if the EMIB connection wasn’t thermally stable to withstand power-cycling between two dies.

Intel in a blog posted that its latest semiconductor and packaging technologies used to make the Stratix 10 GX 10M FPGA are just the start of the market-visible benefits we will see.